1. Field of the Invention
The present invention is related to a semiconductor device, and more particularly, to a CMOS (Complementary Metal Oxide Semiconductor) device and a method for fabricating the same which has improved operation speed and reliability.
2. Discussion of the Related Art
There have been ceaseless efforts in fabrication of a semiconductor integrated circuit for reducing a size of an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which can provide a highly integrated high performance semiconductor chip. The size has been scaled down to a sub-micron level. The size reduction of the semiconductor device should be both in horizontal and vertical directions for balancing with various device characteristics. That is, in the device size reduction, for example, if a distance between a source and a drain comes closer in a transistor, undesirable changes in the characteristics of device occur, e.g., the short channel effect. In order to improve the short channel effects in a high density device, an LDD (Lightly Doped Drain) structure is employed, in which low concentration junctions are formed under sidewalls of a gate.
FIG. 1 illustrates an equivalent circuit for a background art CMOS invertor.
In general, as shown in FIG. 1, the background art CMOS invertor is provided with an NMOS transistor Q1 and a PMOS transistor Q2. The NMOS transistor Q1 and PMOS transistor Q2 are connected in series, with their gates receiving an input signal Vin in common. A drain of the NMOS transistor Q1 is connected to a ground terminal Vss; a source of the PMOS transistor Q2 is adapted to be supplied with a static voltage Vdd, and connection terminals of the NMOS transistor Q1 and the PMOS transistor Q2 are provided as an output terminal Vout.
A background art CMOS device and a method for fabricating the same will be explained with reference to the attached drawings. FIG. 2 illustrates a section of the background art CMOS device.
Referring to FIG. 2, the background art CMOS transistor is provided with an n-well 12 and a p-well 13 formed in surfaces of the semiconductor substrate 11, field oxide films 14 formed in isolating region and field regions of the n-well 12 and the p-well 13, first and second gate electrodes 16a and 16b formed on the gate insulating film 15 in active regions of the n-well 12 and the p-well 13 isolated by the field oxide film 14, insulating film sidewalls 22 at both sides of the first and second gate electrodes 16a and 16b respectively, and heavily doped p type impurity regions 24 and heavily doped n type impurity regions 26, both with LDD structures, in surfaces of the semiconductor substrate 11 on both sides of the first and second gate electrodes 16a and 16b respectively.
FIGS. 3A to 3I illustrate sections showing the steps of a background art method for fabricating a CMOS device.
Referring to FIG. 3A, n type impurity ions and p type impurity ions are selective injected into predetermined regions of a semiconductor substrate 11 and subjected to drive in diffusion, to form an n-well 12 and a p-well 13 in surfaces of the semiconductor substrate 11. Then, an initial oxide film and a nitride film are formed in succession on an entire surface of the semiconductor substrate 11, subjected to photolithography and etching to remove the nitride film selectively to define field regions and active regions, and an LOCOS (local oxidation of silicon) is conducted to form field oxide films 14 on an interface region of the n-well 12 and the p-well 13 and field regions.
As shown in FIG. 3B, a gate insulating film 15 and a gate electrode polysilicon layer 16 are formed on an entire surface of the semiconductor substrate 11 inclusive of the field oxide films 14. Then, a first photoresist film 17 is formed on the polysilicon layer 16 and subjected to exposure and development for patterning the first photoresist film 17. As shown in FIG. 3C, the polysilicon layer 16 and the gate insulating film 15 are selectively removed using the patterned photoresist film 17 as a mask, to form first and second gate electrodes 16a and 16b in active regions on the n-well 12 and the p-well 13.
As shown in FIG. 3D, the first photoresist film 17 is removed, and a second photoresist film 18 is coated on an entire surface of the semiconductor substrate 11 inclusive of the first, and second gate electrodes 16a and 16b and subjected to patterning by exposure and development, to leave the second photoresist film 18 only over the p-well 13 region. Then, p type impurities are lightly injected into an entire surface of the semiconductor substrate 11 using the patterned second photoresist film 18 as a mask, to form first LDD (Lightly Doped Drain) regions 19 in surfaces of the semiconductor substrate 11 on both sides of the first gate electrode 16a. 
As shown in FIG. 3E, the second photoresist film 18 is removed, and a third photoresist film 20 is coated on an entire surface of the semiconductor substrate 11 inclusive of the first, and second gate electrodes 16a and 16b and subjected to patterning by exposure and development, to leave the third photoresist film 20 only over the n-well region 12. Then, n type impurities are injected into an entire surface of the semiconductor substrate 11 using the patterned third photoresist film 20 as a mask, to form second LDD regions 21 in surfaces of the semiconductor substrate 11 on both sides of the second gate electrode 16b. 
As shown in FIG. 3F, the third photoresist film 20 is removed, and an insulating film is formed on an entire surface of the semiconductor substrate 11 inclusive of the first, and second gate electrodes 16a and 16b and is etched back, to form insulating film sidewalls 22 at both sides of the first, and second gate electrodes 16a and 16b. 
As shown in FIG. 3G, a fourth photoresist film 23 is coated on an entire surface of the semiconductor substrate 11 inclusive of the first and second gate electrodes 16a and 16b and subjected to patterning by exposure and development to leave the fourth photoresist film 23 only over the n-well region. Then, source/drain p type impurities are heavily injected into an entire surface of the semiconductor substrate using the patterned fourth photoresist film 23 as a mask, to form heavily doped p type impurity regions 24 connected to the first LDD regions 19 in surfaces of the semiconductor substrate 11 on both sides of the first gate electrode 16a. The first gate electrode 16a and the heavily doped p type impurity regions 24 form a PMOS device.
As shown in FIG. 3H, the fourth photoresist film 23 is removed, and a fifth photoresist film 25 is coated on an entire surface of the semiconductor substrate 11 inclusive of the first and second gate electrodes 16a and 16b and subjected to patterning by exposure and development, to leave the fifth photoresist film 25 only over the p-well region 21. Then, source/drain n type impurities are heavily injected into an entire surface of the semiconductor substrate 11 using the patterned fifth photoresist film 25 as a mask, to form heavily doped n type impurity regions 26 connected to the second LDD regions 21 in surfaces of the semiconductor substrate 11 on both sides of the second gate electrode 16b. The second gate electrode 16b and the heavily doped impurity regions 26 on both sides thereof form an NMOS device.
As shown in FIG. 3I, by removing the fifth photoresist film 25, fabrication of a CMOS device formed with an NMOS device and a PMOS device on an n-well 12 and a p-well 13 in a semiconductor substrate 11 respectively is completed.
However, the background art CMOS device and a method for fabricating the CMOS device have the following problems.
First, the hot carrier effect caused by junction capacitances between the source/drain regions increases as device size is scaled down to a sub-micron level, which degrades performance and reliability of the device.
Second, latch-up occurs between the NMOS and the PMOS transistors and this degrades device performance.
Third, the uneven surface coming from the formation of the NMOS and the PMOS transistors causes difficulty in formation of wiring.
Accordingly, the present invention is directed to a CMOS device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a CMOS device and a method for fabricating the same, in which junction capacitances and parasitic capacitances are eliminated for improving device operation speed and planarizing of wiring.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the CMOS device includes an insulating film formed on a substrate, first and second sapphire patterns formed on the insulating film at fixed intervals, first and second semiconductor layers formed on the first and second sapphire patterns, isolating films formed between the first and second sapphire patterns and the first and second semiconductor layers, respectively, first and second trenches formed down to predetermined depths from surfaces of the first and second semiconductor layers, sidewall spacers formed at both sides of the first an second trenches, a gate insulating film formed on a surface of each of the first and second semiconductor layers between the sidewall spacers, first and second gate electrodes formed in the first and second trenches respectively on the gate insulating film first conductivity type impurity regions formed in the first semiconductor layer on both sides of the first gate electrodes, and second conductivity type impurity regions formed in the second semiconductor layer on both sides of the second gate electrodes.
In other aspect of the present invention, there is provided a method for fabricating a CMOS device, including the steps of (1) forming an insulating film on a substrate, (2) forming first, and second sapphire patterns on the insulating film at fixed intervals, (3) forming first and second semiconductor layers on the first and second sapphire patterns, respectively, (4) forming isolating films between the first and second sapphire pasterns and the first and second semiconductor layers and at opposite sides, (5) forming first, and second trenches in surfaces of the first, and second semiconductor layers to predetermined depths, respectively, (6) forming sidewall spacers at both sides of the first and second trenches, respectively, (7) forming a gate insulating film on a surface of each of the first and second semiconductor layers in the first and second trenches, (8) forming first, and second gate electrodes on the gate insulating film, (9) forming a second conductivity type impurity regions in the first semiconductor layer on both sides of the first gate electrode, and (10) forming a first conductivity type impurity regions in the second semiconductor layer on both sides of the second gate electrode.